Solving the New Challenges of PIC Wafer Inspection with UFO Probe Card®
Jenoptik's UFO Probe® Card is a test solution that enables parallel testing using existing test infrastructure.
Testing PICs with Wafer Level Tests
Wafer-Level test, wafer sort and wafer final test are conducted using wafer probers and automatic test equipment, also known as testers. The electrical contacting of the chips on the wafer is achieved through the use of probe cards, which employ microscopic needles to establish electrical contact with the interfaces on the die (bond pads or solder bumps). This technology also allows for the contact and testing of all chips on a 300 mm wafer simultaneously with a single probe card. Probe cards are then manufactured with several tens to hundreds of thousands of needles and are typically used for memory devices.
In addition to the electrical contacts, photonic integrated circuits also feature optical interfaces. These can be either grating couplers which are arranged on the chip’s surface, analogous to electrical contact pads, or alternatively, edge couplers which are used where the actual waveguide ends at the edge of the respective chip (their light is coupled into the device).
The combination of electrical and optical functionalities on a PIC presents a challenge when aligning the wafer to the probe card and thus testing. Electrical contacts are relatively large, ranging in sizes up to 150 µm in diameter or sometimes even larger. Consequently, commercially available wafer probers, which were originally designed for electrical testing, have a positioning tolerance of between 1.5 and 4 µm in the lateral direction. However, to ensure stable optical coupling, it is essential to position the wafer in close proximity to the illumination unit (e.g., optical fibres) of the test system, ensuring that it is well below the mode field diameter (MFD) of the optical interfaces of the chips. Typical values for the MFD of grating couplers are 10 µm, while for edge couplers, it is in the range of 1-2 µm. Therefore, a positioning accuracy in the sub-micron range is necessary to achieve optimal results.
The testing process varies depending on the type of integration of the PICs. In the case of heterogeneously integrated PICs, the optical wafers and the driver chips (ASICs) are manufactured according to their own individual process, which also includes wafer testing. In the case of monolithic-assembled PICs, the electronics are already integrated into the chip, which makes wafer-level testing a critical step. Wafer maps with known-good-dies (KGD) provide valuable information about the quality of the chips at an early stage, helping to identify rejects. This process enables higher yields and reduces overall costs.
Testing with UFO Probe® Card
Jenoptik's UFO Probe® Card takes a different approach to testing. Here, an optical and an electrical probe module are monolithically integrated on a single probe card. The patented technology includes an optical concept that does not require active alignment of the optical interfaces for each die. It can be used on existing IC test equipment like a standard prober, overcoming technical limitations such as different position tolerances of optical and electrical components. In this way, it enables the time-saving parallel testing of both optical and electrical components on a chip.
Benefits of the UFO Probe® Card:
- Faster PIC testing: Patented optical concept allows optical and electrical probes to combine in one instrument
- Reduced test time per wafer: No active alignment time required on each die, only once on each wafer
- Increase overall yield: Identification of known good dies early in the production process
- Plug & Play for easy integration: runs on existing standard IC wafer probers and automated test equipment
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